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AIWA ICDP200 Y
Service Manual


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  • Contains Circuit Diagrams
  • Download
  • PDF Format
  • Complete manual
  • Language: English
Price: $4.99

Description of AIWA ICDP200 Y Service Manual

Complete service manual in digital format (PDF File). Service manuals usually contains circuit diagrams, printed circuit boards, repair tips, wiring diagrams, block diagrams and parts list. Service Manual ( sometimes called Repair Manual ) is used mainly by technicians.

If You just want to know how to use Your tv, video, mp3 player etc. You should look for Owner's Manual. After placing order we'll send You download instructions on Your email address.

The manual is available in languages: English

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Text excerpt from page 23 (click to view)
Pin No.
17 18 19 ~ 26 27 28 29 30 31 32 33

Pin Name
FODD HREF UV7 ~ UV0 XCLK1 XCLK2 DVDD DGND DOGND DOVDD PCLK

I/O
O O O I O – – – – O

Description
FODD: Odd field flag. Asserted high during the odd field, low during the even field. (Not used) HREF: Horizontal window reference output. HREF is high during the active pixel window, otherwise low. UVn: Digital output UV bus. UVn used for 16-bit operation for outputting chrominance data. XCLK1 and XCLK2 are the input/output of the on-chip video oscillator. Nominal crystal clock frequency is 27MHz. If an external clock is used, input to XCLK1, leave XCLK2 unconnected. (XCLK2 = Not used) Digital power (+5V) pin. Digital ground connection. Digital output ground connection. Digital I/O power (+5V) pin. PCLK: Pixel clock output. By default, data is updated at the falling edge of PCLK and is stable at its rising edge. PCLK runs at the pixel rate in 16-bit bus operations and twice the pixel rate in 8-bit bus operations. Yn: Digital output Y bus. In a 16-bit operation, the luminance data is clocked out of this bus

34 ~ 41 42 43 44 45 46 47 48

Y7 ~ Y0 CHSYNC AGND AVDD SCL SDA MID SGND

O O – – I I/O I –

at the rate of one byte per pixel. In 8-bit operation, the luminance data and the chrominance data is multiplexed to this bus. CHSYNC: Digital output for either composite sync or horizontal sync signal. Analog ground connection. Analog power (+5V) pin. I2C serial clock input with schmitt trigger. I2C serial data, output is open-drain, input with schmitt trigger. Multiple I2C slave ID enable. (Not used) Sensing ground connection

IC, PCF8576CH Pin No.
1 2~7 8~9 10 11 12 13 14 15 16 ~ 18 19 20

Pin Name
NC S34 ~ S39 NC SDA SCL SYNC CLK VDD OSC A0 ~ A2 SA0 VSS

I/O
– O – I/O I I/O I – I I I – Not connected. LCD segment outputs. (Not used) Not connected. I2C bus serial data input/output. I2C bus serial clock input.

Description

Cascade synchronization input/output. (Not used) External clock input. (Not used) Supply voltage. Oscillator input. (Connected to VSS) I2C bus subaddress inputs. (Connected to VSS) I2C bus slave address input, bit 0. (Connected to VSS) Logic ground.

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