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AIWA CSDA170K
Service Manual


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  • Contains Circuit Diagrams
  • Download
  • PDF Format
  • Complete manual
  • Language: English
Price: $4.99

Description of AIWA CSDA170K Service Manual

Complete service manual in digital format (PDF File). Service manuals usually contains circuit diagrams, printed circuit boards, repair tips, wiring diagrams, block diagrams and parts list. Service Manual ( sometimes called Repair Manual ) is used mainly by technicians.

If You just want to know how to use Your tv, video, mp3 player etc. You should look for Owner's Manual. After placing order we'll send You download instructions on Your email address.

The manual is available in languages: English

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Text excerpt from page 17 (click to view)
IC DESCRIPTION IC, LA9241ML
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Name FIN2 FIN1 E F TB TETE TESI SCI TH TA TDTD JP TO FD FDI/O I I I I I I O I I I O I I I O O I Description Pin to which external pickup photo diode is connected. RF signal is created by adding with the FIN1 pin signal. FE signal is created by subtracting from the FIN1 pin signal. 37 Pin to which external pickup photo diode is connected. Pin to which external pickup photo diode is connected. TE signal is created by subtracting from the F pin signal. Pin to which external pickup photo diode is connected. DC component of the TE signal is input. Pin to which external resistor setting the TE signal gain is connected between the TE pin. 43 TE signal output pin. TES “Track Error Sense” comparator input pin. TE signal is passed through a bandpass filter then input. Shock detection signal input pin. Tracking gain time constant setting pin. TA amplifier output pin. Pin to which external tracking phase compensation constants are connected between the TD and VR pins. Tracking phase compensation setting pin. Tracking jump signal (kick pulse) amplitude setting pin. Tracking control signal output pin. Focusing control signal output pin. Pin to which external focusing phase compensation constants are connected between the FD and FA pins. 18 FA I Pin to which external focusing phase compensation constants are connected between the FD– and FA– pins. 19 20 21 22 23 24 25 26 27 28 29 30, 31 32, 33 34 35 FAFE FEAGND SP SPI SPG SPSPD SLEQ SLD SL-, SL+ JP-, JP+ TGL TOFF I O I — O I I I O I O I I I I Pin to which external focusing phase compensation constants are connected between the FA and FE pins. FE signal output pin. Pin to which external FE signal gain setting resistor is connected between the FE pin. Analog signal GND. Signal ended output of the CV+and CV- pin input signal. Spndle amp input. Pin to which external spindle gain setting resistor in 12 cm mode is connected. Pin to which external spindle phase compensation constants are connected together with SPD pin. Spindle control signal output pin. Pin to which external sled phase compensation constants are connected. Sled control signal output pin. Sled advance signal input pin from microprocessor. Tracking jump signal input pin from DSP. Tracking gain control signal input from DSP. Low gain when TGL = H. Tracking off control signal input pin from DSP. Off when TOFF = H. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SLI DGND FSC TBC NC DEF CLK CL DAT CE DRF FSS VCC2 REFI VR LF2 PH1 BH1 LDD LDS VCC1 I — O I — O I I I I O I — — O I I I O I — SLC O DSP. Input pin which control the data slice level by the DSP. Digital system GND. Output pin to which external focus search smoothing capacitor is connected. “Tracking Balance Control” EF balance variable range setting pin. No connection. Disc defect detector output pin. Reference clock input pin. 4.23 MHz of the DSP is input. Microprocessor command clock input pin. Microprocessor command data input pin. Microprocessor command chip enable input pin. “Detect RF” RF level detector output. “Focus Search Select” focus search mode (± search/+ search) select pin. Servo system and digital system Vcc pin. Pin to which external bypass capacitor for reference voltage is connected. Reference voltage output pin. Disc defect detector time constant setting pin. Pin to which external capacitor for RF signal peak holding is connected. Pin to which external capacitor for RF signal bottom holding is connected. APC circuit output pin. APC circuit input pin. RF system Vcc pin. 38 39, 40 41 42 SLOF CV–, CV+ RFSM RFSI I O I HFL O bit or on top of mirror. Sled servo off control input pin. CLV error signal input pin from DSP. RF output pin. RF gain setting and EFM signal 3T compensation constant setting pin together with RFSM pin. “Slice Level Control” is the output pin which controls the RF signal data slice level by Pin No. 36 Pin Name TES I/O O Description Pin from which TES signal is output to DSP. “High Frequency Level” is used to judge whether the main beam position is on top of

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